sv2v for Mac

sv2v: SystemVerilog to Verilog

sv2v converts SystemVerilog ([IEEE 1800-2017]) to Verilog ([IEEE 1364-2005]), with an emphasis on supporting synthesizable language constructs.

The primary goal of this project is to create a completely free and open-source tool for converting SystemVerilog to Verilog. While methods for performing this conversion already exist, they generally either rely on commercial tools, or are limited in scope.

This project was originally developed to target [Yosys], and so allows for disabling the conversion of (passing through) those [SystemVerilog features that Yosys supports].

The idea for this project was shared with me while I was an undergraduate at Carnegie Mellon University as part of a joint Computer Science and Electrical and Computer Engineering research project on open hardware under Professors [Ken Mai] and [Dave Eckhardt]. I have greatly enjoyed collaborating with the team at CMU since January 2019, even after my graduation the following May.

Dependencies

All of sv2v's dependencies are free and open-source.

Build Dependencies Haskell Stack - Haskell build system Haskell dependencies are managed in sv2v.cabal Test Dependencies Icarus Verilog - for Verilog simulation shUnit2 - test framework Python 3.x - for evaluating certain test cases

Installation

Pre-built binaries

Binaries for Ubuntu, macOS, and Windows are available on the [releases page]. If your system is not covered, or you would like to build the latest commit, simple instructions for building from source are below.

Building from source

You must have [Stack] installed to build sv2v. Then you can:

This creates the executable at ./bin/sv2v. Stack takes care of installing exact (compatible) versions of the compiler and sv2v's build dependencies.

You can install the binary to your local bin path (typically ~/.local/bin) by running stack install, or copy over the executable manually.

Usage

sv2v takes in a list of files and prints the converted Verilog to stdout by default. Users should typically pass all of their SystemVerilog source files to sv2v at once so it can properly resolve packages, interfaces, type parameters, etc., across files. Using --write=adjacent will create a converted .v for every .sv input file rather than printing to stdout. --write/-w can also be used to specify a path to a .v output file. Undefined modules and interfaces can be automatically loaded from library directories using --libdir/-y.

Users may specify include search paths, define macros during preprocessing, and exclude some of the conversions. Specifying - as an input file will read from stdin.

Below is the current usage printout.

Supported Features

sv2v supports most synthesizable SystemVerilog features. Current notable exceptions include defparam on interface instances, certain synthesizable usages of parameterized classes, and the bind keyword. Assertions are also supported, but are simply dropped during conversion.